Struct kernel::a53::gicv2::DistributorRegisterBlock

source · 
#[repr(C)]
pub struct DistributorRegisterBlock {
Show 26 fields
    pub ctlr: Register<GICD_CTLR>,
    pub typer: Register<u32>,
    pub iidr: Register<u32>,
    _0: [Register<u8>; BYTES],
    _1: [Register<u8>; BYTES],
    _2: [Register<u8>; BYTES],
    pub igroupr: [Register<u32>; 32],
    pub isenabler: [Register<GICD_ISENABLER>; 32],
    pub icenabler: [Register<u32>; 32],
    pub ispender: [Register<u32>; 32],
    pub icpendr: [Register<u32>; 32],
    pub isactiver: [Register<u32>; 32],
    pub icactiver: [Register<u32>; 32],
    pub ipriorityr: [Register<u32>; 255],
    _3: [Register<u8>; BYTES],
    pub itargetsr: [Register<u32>; 255],
    _4: [Register<u8>; BYTES],
    pub icfgr: [Register<u32>; 64],
    _5: [Register<u8>; BYTES],
    pub nsacr: [Register<u32>; 64],
    pub sgir: Register<u32>,
    _6: [Register<u8>; BYTES],
    pub cpendsgir: [Register<u32>; 4],
    pub spendsgi: [Register<u32>; 4],
    _7: [Register<u8>; BYTES],
    _8: [Register<u8>; BYTES],

}

Fields§

§ctlr: Register<GICD_CTLR>

0x000: GICD_CTLR (Distributor Control Register)

§typer: Register<u32>

0x004: GICD_TYPER (Interrupt Controller Type Register)

§iidr: Register<u32>

0x008: GICD_IIDR (Distributor Implementer Identification Register)

§_0: [Register<u8>; BYTES]

0x00C-0x01C: Reserved

§_1: [Register<u8>; BYTES]

0x020-0x03C: IMPLEMENTATION DEFINED registers

§_2: [Register<u8>; BYTES]

0x040-0x07C: Reserved

§igroupr: [Register<u32>; 32]

0x080: GICD_IGROUPRnb (Interrupt Group Registers)

§isenabler: [Register<GICD_ISENABLER>; 32]

0x100-0x17C: GICD_ISENABLERn (Interrupt Set-Enable Registers)

§icenabler: [Register<u32>; 32]

0x180-0x1FC: GICD_ICENABLERn (Interrupt Clear-Enable Registers)

§ispender: [Register<u32>; 32]

0x200-0x27C: GICD_ISPENDRn (Interrupt Set-Pending Registers)

§icpendr: [Register<u32>; 32]

0x280-0x2FC: GICD_ICPENDRn (Interrupt Clear-Pending Registers)

§isactiver: [Register<u32>; 32]

0x300-0x37C: GICD_ISACTIVERn (GICv2 Interrupt Set-Active Registers)

§icactiver: [Register<u32>; 32]

0x380-0x3FC: GICD_ICACTIVERn (Interrupt Clear-Active Registers)

§ipriorityr: [Register<u32>; 255]

0x400-0x7F8: GICD_IPRIORITYRn (Interrupt Priority Registers)

§_3: [Register<u8>; BYTES]

0x7FC: Reserved

§itargetsr: [Register<u32>; 255]

0x800-0x81C: GICD_ITARGETSRn (Interrupt Processor Targets Registers)

§_4: [Register<u8>; BYTES]

0xBFC: Reserved

§icfgr: [Register<u32>; 64]

0xC00-0xCFC: GICD_ICFGRn (Interrupt Configuration Registers)

§_5: [Register<u8>; BYTES]

0xD00-0xDFC: IMPLEMENTATION DEFINED registers

§nsacr: [Register<u32>; 64]

0xE00-0xEFC: GICD_NSACRn (Non-secure Access Control Registers, optional)

§sgir: Register<u32>

0xF00: GICD_SGIR (Software Generated Interrupt Register)

§_6: [Register<u8>; BYTES]

0xF04-0xF0C: Reserved

§cpendsgir: [Register<u32>; 4]

0xF10-0xF1C: GICD_CPENDSGIRn (SGI Clear-Pending Registers)

§spendsgi: [Register<u32>; 4]

0xF20-0xF2C: GICD_SPENDSGIRn (SGI Set-Pending Registers)

§_7: [Register<u8>; BYTES]

0xF30-0xFCC: Reserved

§_8: [Register<u8>; BYTES]

0xFD0-0xFFC: - ( Identification registers on page 4-119)

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