Struct kernel::a53::pl011::Pl011RegisterBlock

source · 
#[repr(C)]
pub struct Pl011RegisterBlock {
Show 22 fields
    pub dr: Register<UARTDR>,
    pub rsr_ecr: Register<u32>,
    _0: [Register<u8>; BYTES],
    pub fr: Register<u32>,
    _1: [Register<u8>; BYTES],
    pub ilpr: Register<u32>,
    pub ibrd: Register<u32>,
    pub fbrd: Register<u32>,
    pub lcr_h: Register<u32>,
    pub cr: Register<u32>,
    pub ifls: Register<u32>,
    pub imsc: Register<u32>,
    pub ris: Register<u32>,
    pub mis: Register<u32>,
    pub icr: Register<u32>,
    pub dmacr: Register<u32>,
    _2: [Register<u8>; BYTES],
    _3: [Register<u8>; BYTES],
    _4: [Register<u8>; BYTES],
    _5: [Register<u8>; BYTES],
    pub periph_id: [Register<u32>; 4],
    pub p_cell_id: [Register<u32>; 4],

}

Fields§

§dr: Register<UARTDR>

0x000: UARTDR (Data Register)

§rsr_ecr: Register<u32>

0x004: UARTRSR/UARTECR (Receive Status Register/Error Clear Register)

§_0: [Register<u8>; BYTES]

0x008-0x014: Reserved

§fr: Register<u32>

0x018: UARTFR (Flag Register)

§_1: [Register<u8>; BYTES]

0x01C: Reserved

§ilpr: Register<u32>

0x020: UARTILPR (IrDA Low-Power Counter Register)

§ibrd: Register<u32>

0x024: UARTIBRD (Integer Baud Rate Register)

§fbrd: Register<u32>

0x028: UARTFBRD (Fractional Baud Rate Register)

§lcr_h: Register<u32>

0x02C: UARTLCR_H (Line Control Register)

§cr: Register<u32>

0x030: UARTCR (Control Register)

§ifls: Register<u32>

0x034: UARTIFLS (Interrupt FIFO Level Select Register)

§imsc: Register<u32>

0x038: UARTIMSC (Interrupt Mask Set/Clear Register)

§ris: Register<u32>

0x03C: UARTRIS (Raw Interrupt Status Register)

§mis: Register<u32>

0x040: UARTMIS (Masked Interrupt Status Register)

§icr: Register<u32>

0x044: UARTICR (Interrupt Clear Register)

§dmacr: Register<u32>

0x048: UARTDMACR (DMA Control Register)

§_2: [Register<u8>; BYTES]

0x04C-0x07C: Reserved

§_3: [Register<u8>; BYTES]

0x080-0x08C: Reserved for test purposes

§_4: [Register<u8>; BYTES]

0x090-0xFCC: Reserved

§_5: [Register<u8>; BYTES]

0xFD0-0xFDC: Reserved for future ID expansion

§periph_id: [Register<u32>; 4]

0xFE0: UARTPeriphID0; 0xFE4: UARTPeriphID1; 0xFE8: UARTPeriphID2; 0xFEC: UARTPeriphID3

§p_cell_id: [Register<u32>; 4]

0xFF0: UARTPCellID0; 0xFF4: UARTPCellID1; 0xFF8: UARTPCellID2; 0xFFC: UARTPCellID3

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